1. Field of the Invention
The present invention generally relates to computer systems which include memory devices that are subject to read and write transactions by a central processing unit (CPU) or other system device. Still more particularly, the present invention relates to a computer system implementation in which data is transferred between memory and the CPU in bursts Still more particularly, the present invention relates to a system in which the burst length of the data stream can be modified based upon a variety of criteria to improve the efficiency of the computer system.
2. Description of the Relevant Art
For most computer systems, the number of clock cycles required for a data access to a memory device depends upon the component accessing the memory and the speed of the memory unit. Most of the memory devices in a computer system are slow relative to the clock speed of the central processing unit (CPU). As a result, the CPU is forced to enter wait states when seeking data from the slower memory devices. Because of the relative slowness of most memory devices, the efficiency of the CPU can be severely compromised. As the operating speed of processors increases and as new generations of processors evolve, it is advantageous to minimize wait states in memory transactions to fully exploit the capabilities of these new processors.
One technique which has been used and which has gained widespread acceptance in computer systems is the use of one or more high speed cache memory devices. Typically, the cache memory is placed intermediate the CPU and system memory, and is used to store frequently used, or recently used, data. While cache memory devices have reduced processor latency times in memory transactions, a problem still exist with latency in memory transactions, especially for memory transactions to other memory sub-systems, such as the system memory.
Another technique which has been used to reduce processor latency in memory transactions is to increase the amount of information transferred in each memory access. Protocols exist for bursting data streams under certain conditions in some systems, such as the PCI (Peripheral Component Interconnect) bus. The PCI bus has a protocol which permits data to be transferred in a burst mode.
The burst mode feature allows reads or writes to consecutive memory locations at high speed, via burst cycles. The normal procedure for reading or writing from memory is that the CPU in a first clock cycle generates the address signals on the address bus, and then in the following clock cycle, data is transferred to or from system memory. Since the PCI data bus, for example, is 32-bits wide, a total of four bytes (each byte has 8 bits) of data can be read or written by the CPU for every two clock cycles. Each set of four bytes transferred on the data bus is referred to as a "double word." In burst mode, additional sequential double words may be transferred during subsequent clock cycles without intervening address phases. For example, a total of four double words can be read into the CPU using only five clock cycles because only the starting address is sent out on the address bus, and subsequently the first double word of data is read during the second cycle, the next double word of data during the third cycle, and so on. Thus, where a normal transfer of four double words would take at least eight clock cycles, the burst mode permits four doublewords to be transferred in five clock cycles. Burst mode operation thereby accommodates relatively high data transfer rates, and significantly reduces the latency involved in a memory transfer.
Despite the advantages of operating in burst mode, the burst mode feature has certain limitations. One limitation inherent in burst mode transfers is that the burst mode length typically is fixed, and cannot be altered. In addition, the burst mode feature is not responsive to actual latency conditions in the system. In the devices and busses which use burst mode transactions, the burst length typically is fixed by the system designer. The optimal burst length value, however, is dependent upon a number of factors that typically are not known during the design process. Consequently, a system designer does not have all of the information necessary to make a fully informed decision regarding the optimal burst length for a particular memory device.